Spi Serial Flash Programmer Schematic Design

Jun 2, 2015 - FlashProg: USB serial flash memory programmer. Base flash memory programmer which is specifically design to read and program 3.3V SPI flash memory devices. FlashProg programmer schematic is illustrated in below. At the moment it supports I²C Bus, Microwire, SPI eeprom, the Atmel AVR and Microchip PIC micro. SI-Prog is the programmer hardware interface for PonyProg. With PonyProg and SI-Prog you can program Wafercard for SAT, eeprom within GSM, TV or CAR-RADIO.

The Generic Serial Flash Interface Intel ® FPGA IP core provides access to Serial Peripheral Interface (SPI) flash devices. The Generic Serial Flash Interface IP is a more efficient alternative compared to the ASMI Parallel and ASMI Parallel II Intel ® FPGA IP cores. The Generic Serial Flash Interface Intel ® FPGA IP core supports Intel ® configuration devices as well as flash from different vendors. Intel ® recommends you to use the Generic Serial Flash Interface Intel ® FPGA IP core for new designs.

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Ports Description Signal Width Direction Description Avalon ®-MM slave interface for CSR (avl_csr) avl_csr_addr 6 Input Avalon ®-MM address bus. The address bus is in word addressing. Avl_csr_read 1 Input Avalon ®-MM read control to the CSR. Avl_csr_rddata 32 Output Avalon ®-MM read data bus from the CSR.

Avl_csr_write 1 Input Avalon ®-MM write control to the CSR. Avl_csr_wrdata 32 Input Avalon ®-MM write data bus to CSR.

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Avl_csr_waitrequest 1 Output Avalon ®-MM waitrequest control from the CSR avl_csr_rddata_valid 1 Output Avalon ®-MM read data valid that indicates the CSR read data is available. Avalon ®-MM slave interface for memory access (avl_ mem) avl_mem_write 1 Input Avalon ®-MM write control to the memory avl_mem_burstcount 7 Input Avalon ®-MM burst count for the memory.

The value range from 1 to 64 (Max page size). Avl_mem_waitrequest 1 Output Avalon ®-MM waitrequest control from the memory. Avl_mem_read 1 Input Avalon ®-MM read control to the memory avl_mem_addr N Input Avalon ®-MM address bus. The address bus is in word addressing. The width of the address depends on the flash memory density.If you are using Intel ® Arria ® 10, and Intel ® Cyclone ® 10 GX or any supported devices with general purpose I/O with multiples flashes, write the CSR to select the chip select. The IP targets the selected flash when being accessed via this address.

Avl_mem_wrdata 32 Input Avalon ®-MM write data bus to the memory avl_mem_readddata 32 Output Avalon ®-MM read data bus from the memory. Avl_mem_rddata_valid 1 Output Avalon ®-MM read data valid that indicates the memory read data is available. Avl_mem_byteenble 4 Input Avalon ®-MM write data enable bus to memory. During bursting mode, byteenable bus will be logic high, 4’b1111. Clock and Reset clk 1 Input Input clock to clock the IP core.

Reset 1 Input Asynchronous reset to reset the IP core. Interrupt Irq 1 Output Interrupt signal that indicate if there is an illegal write or illegal erase. Conduit Interface flash_data 4 Bidirectional Input or output port to feed data from the flash device. Flash_dclk 1 Output Provides clock signal to the flash device. Flash_ncs 1/3 Output Provides the ncs signal to the flash device. Parameter Settings Parameter Legal Values Descriptions Device Density 1, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024, 2048 Density of the flash device used in Mb. Disable dedicated Active Serial interface — Routes the signals to the top level of your design.

Enable this when you want to include the Serial Flash Loader Intel FPGA IP in your design. Enable SPI pins interface — Translates the signals to the SPI pin interface.

Number of Chip Select used 1 2 3 Selects the number of chip select connected to the flash. Enable flash simulation model — Uses the flash inside the device for simulation model. Register Map. Register Map • Each address offset in the following table represents 1 word of memory address space. • IP_CLK is the clock that drives the IP • SCLK is the clock that drives the flash device Offset (Hex) Register Name R/W Field Name Bit Default Value (Hex) Description 0 Control Register Reserved 31:8 Reserved R/W Addressing mode 8 0x0 Addressing mode for read and write operation: • 0x0: 3-bytes addressing • 0x1: 4-bytes addressing For 4-byte addressing mode, you must enable 4-byte address by sending command to the flash.This bit affects direct access to memory via the Avalon-MM interface for both write and read operation. R/W Chip select 7:4 0x0 Selects the flash device • 0x0: To select first device • 0x1: To select second device • 0x2: To select third device Reserved 3:1 Reserved R/W Enable 0 0x1 Set this bit to 0 to disable the output of the IP and put all output signal to high impedance state. This can be used to share bus with other devices.